A Traditional CPU Architecture

Are you familiar with the Zilog Z80 CPU? Suppose we expand its general purpose registers to hold 16 bits each, instead of 8. Also, suppose each memory address now holds 16 bits too, instead of the usual 8 (bye bye bytes). With these two assumptions in mind, what sort of CPU architecture can we make that is wildly similar to the Z80?

Please note that this is very easy to adapt to 32-bits data registers and 64-bits address registers.

The Registers

First of all, let's see the registers that are available to the user. We have the usual A, F, B, C, D, E, H, and L. Each holds 16 bits. The register F is the flags register. Then we have the 32-bit registers IX and IY, used for indexed addressing. Finally, we have the SP, or stack pointer, and also the program pointer, named PP. These last two registers also hold 32 bits. Let's call 16 bits a word. Thus, 32-bit registers contain an address of memory that can access 4 gibiwords (or 8 gibibytes).

The processor is always little-endian.

General Instructions

Each instruction is 16 bits wide followed or not by 16 more bits or perhaps 32, as required, for the instruction to make sense.

NOP

Do nothing.

CCF

RCF

SCF

Complement carry flag, reset carry flag, and set carry flag.

LDD

LDI

LDDR

LDIR

Load, then decrement or increment, and possibly repeat.

CPD

CPI

CPDR

CPIR

Compare, then decrement or increment, and possibly repeat.

LD dst, (nn)

Load the dst register with the contents of memory at address nn. If bit 3 is zero, it loads 16 bits into B, C, D, E, H, L, (HL), or A. If bit 3 is one, it loads 32 bits into one of BC, DE, HL, or SP. Please refer to the following table for valid values of dst.

LD (nn), src

Load the contents of the register specified by src into the memory location addressed by nn. Again, if bit 3 is zero, 16 bits are transferred, and if it's one, 32 bits are loaded into nn and nn+1. Refer to the dst table in the previous instruction for the valid values of src - they are the same.

LD dst, n

LD dst, nn

Load the register dst with the value n. If dst is a 32-bit register (bit 3 holds the value one), load it with the value nn.

LD dst, src

The operation depends on the values of bits 3 and 7. If both these bits are 0, the operation loads the 16-bit contents of register src into register dst. If bit 7 is 0, and the other is 1, the memory address pointed to by dst is loaded with the contents of register src. In this case, the instruction should be written as LD (dst), src. If, on the other hand, bit 7 is 1 and bit 3 is 0, then register dst is loaded with the memory contents of the address pointed to by src. The instruction should then be written as LD dst, (src). Finally, if both bits are 1, the 32-bit register dst is loaded with the contents of the 32-bit register src. The instruction should in this case be written as LD dst, src.

EX dst, src

Exchange contents of src with that of dst. Again the operation depends on the values of bits 3 and 7. See LD just above for the details. You'll notice there's quite a lot of repeated (like EX A, B and EX B, A) and redundant (like EX A, A) functionality here, which can be removed if it's easier to implement. A similar remark applies to LD above.

ADD dst, src

ADC dst, src

SUB dst, src

SBC dst, src

Add dst with src and place the result in dst; add with carry; subtract; and subtract with carry. See LD above for details about src and dst.

MULLU dst, src

MULL dst, src

MULHU dst, src

MULH dst, src

DIVU dst, src

DIV dst, src

REMU dst, src

REM dst, src

MULLU performs an unsigned multiplication between dst and src and stores the lower 16 bits of the result in dst. MULHU performs an unsigned multiplication between dst and src and stores the upper 16 bits of the result into dst. MULL and MULH are similar, only they perform signed multiplication. DIVU is unsigned division, DIV is signed division (both of dst by src); REMU divides (unsigned) dst by (unsigned) src and stores the remainder of that division in dst, and REM is the signed remainder operation.

AND dst, src

OR dst, src

XOR dst, src

CP dst, src

These are the usual logical operations AND, OR, and XOR, along with the instruction CP, which compares dst with src and updates the flags register accordingly.

BIT bb, dst

CPL bb, dst

RES bb, dst

SET bb, dst

These are the operations on the bits of 16-bit registers (that is, bit 3 is always zero). bb is any bit from 00 to 15. BIT sets the flags according to the value of bit bb in register dst; CPL complements the given bit; RES sets it to zero; and SET sets it to one.

RL dst

RLC dst

RR dst

RRC dst

SLA dst

SLL dst

SRA dst

SRL dst

Bit 3 is always zero, that is, these operations are valid only for 16-bit registers. They are: rotate left, rotate left through carry, rotate right, rotate right through carry, shift left arithmetic, shift left logical, shift right arithmetic, and shift right logical. SLA and SLL perform the same operation.

CPL dst

NEG dst

Bit 3 is always zero, that is, these operations are valid only for 16-bit registers. They are one's complement and two's complement.

BCD dst

Convert the number in dst to binary coded decimal format. The number must be between 0 and 9999, otherwise an overflow occurs. Bit 3 is always zero.

RAND dst

Bit 3 is always zero, that is, this operation is valid only for 16-bit registers. It places a random number in dst. (Similar to the Z80 LD A, R instruction, only here we don't have R).

DEC dst

INC dst

Decrement or increment 16- or 32-bit registers.

PUSH reg

POP reg

Bit 3 is always one, i.e., only 32-bit values can be pushed and popped. The relevant registers are given in the following table.

JR i

JR cc, i

JR dst

JR cc, dst

These are the jump relative instructions. i is a number between -32768 and 32767. dst is a signed 16-bit register, that is, bit 3 is always zero. cc is the condition upon which a jump is taken. It can be any of the following values.

Above and below are used after operations with unsigned numbers, and less and greater with signed ones.

JA nn

JA cc, nn

JA dst

JA cc, dst

The jump absolute instructions require a 32-bit address to jump to, either a literal nn or a register dst (bit 3 is always one, but SP is not valid). The conditions cc are the same as the ones for jump relative, above.

DJNZ i

DJNZ dst

Decrement B and jump if it is not zero to a relative destination: i between -32768 and 32767, or a signed value in dst. Bit 3 of field dst is always zero.

CALL nn

CALL cc, nn

CALL dst

CALL cc, dst

These are the usual CALL instructions. dst is always 32 bits, that is bit 3 is always one, with the exception that SP is not a valid dst.

RET

RET cc

Return from subroutine.

RST pp

This calls the subroutine at memory address related to pp and given by the following table. pp should be written as 0x00, 0x10, 0x20, and so on, not as 0, 1, 2, etc.

IX Instructions

To obtain the IX instructions, simply substitute the bits FE of the previous opcodes from 00 to 01, but only for the instructions that deal with H, L, (HL), and HL. (All others should be invalid or reserved?) The registers dst and src then become as in the following table.

The additional register reg (for PUSH and POP instructions) is as in the following table. Probably, all other values should be invalid or reserved.

IY Instructions

This is the same as the IX instructions, only now bits FE of the instruction opcode contain 10 instead of 01.

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